This application claims a priority on a Japanese patent application, 2001-177519 filed on Jun. 12, 2001, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a frequency conversion circuit and a transmitter. More particularly, the present invention relates to a frequency conversion circuit that changes a frequency of an input signal in accordance with a changing ratio set in advance, and a transmitter using such a frequency conversion circuit.
2. Description of the Related Art
A frequency divider that divides a frequency of an input signal input thereto so as to generate an output signal is used in a case where an original oscillator clock is divided in order to obtain a reference clock, for example. In many cases, as such a frequency divider, a frequency dividing circuit is used for dividing the frequency of the original oscillator clock input thereto by an integer other than zero.
The techniques for dividing the original oscillator clock are used, for example, in a circuit that can generate various frequencies by changing the division ratio. In this way, the frequency of the reference clock that is generated from the original oscillator clock can be changed by changing the setting of the circuit and therefore the circuit scale can be reduced as compared with a case where reference clock generating circuits are respectively provided for all the possible frequencies of the reference clock.
Moreover, in a case where a plurality of kinds of reference clocks are required in a device, the original oscillator clock may be divided by a plurality of frequency dividers.
A Japanese Patent Application Laying-Open No. 5-67998 disclosed a transmitting/receiving apparatus as an exemplary application of frequency-dividing techniques. In this known example, the transmitting/receiving apparatus that can set a digital mode and an analog mode therein includes a frequency divider for generating the reference clock. More specifically, in this example, an original oscillator clock generating circuit generates the original oscillator clock having a frequency corresponding to a common multiple of those of all the required reference clocks, thereby enabling the generation of a plurality kinds of the reference clocks required in the transmitting/receiving apparatus. The respective components in the transmitting/receiving apparatus use the reference clocks obtained by dividing the original oscillator clock by corresponding integers other than zero.
In the case of using the frequency divider that divides the input signal by an integer other than zero, however, it is sometimes difficult to generate a plurality of desired frequencies from one original oscillator clock.
In the application disclosed in the Japanese Patent Application Laying-Open No. 5-67998, for example, in some cases, the frequency of the original oscillator clock, that is the least common multiple of those of the reference clocks required, may be too high to realize. These cases may be caused when the number of the required reference clocks is large, or when a combination of the reference clocks required is special.
Moreover, in another case, it may become necessary to add a new reference clock after completing the fabrication of the apparatus. In this case, when the new reference clock cannot be obtained by dividing the original oscillator clock by an integer other than zero, it is difficult to obtain such a new reference clock without modifying the fabricated apparatus.
Therefore, it is an object of the present invention to provide a frequency conversion circuit and a transmitter, which are capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a frequency conversion circuit for changing a frequency of an input signal to obtain an output signal, comprises: a sum holding unit operable to hold a sum; an integrating unit operable to update the sum by changing the sum by a in one direction at each input of a first predetermined signal based on the input signal, where a is a natural number; and an output signal generating unit operable to output a second predetermined signal as the output signal at each time at which the sum has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a.
The integrating unit may hold the sum to which a is added at each input of the first predetermined signal based on the input signal. In this case, the frequency changing unit further comprises a sum adjusting unit operable to reduce the sum by b*k for every k outputs of the second predetermined signal, where k is a positive integer.
Alternatively, the integrating unit may hold the sum from which a is subtracted at each input of the first predetermined signal based on the input signal. In this case, the frequency conversion circuit further comprises a sum adjusting unit operable to add b*k to the sum for every k outputs of the second predetermined signal, where k is a positive integer.
In the frequency conversion circuit, the integrating unit may update the sum at each of the rising of a pulse signal based on the pulse signal serving as the input signal. Furthermore, in the frequency conversion circuit, the output signal generating unit may output the second predetermined signal in synchronization with the rising of the first predetermined signal.
According to the second aspect of the present invention, a transmitter for use in radio communication, comprises: a reference clock generating circuit operable to change a frequency of an original oscillator clock by means of a frequency conversion circuit included therein to generate a reference clock; and a modulation circuit and a digital-analog converter that use the reference clock output from the reference clock generating circuit. In this transmitter, the frequency conversion circuit includes: a sum holding unit operable to hold a sum; an integrating unit operable to update the sum by changing the sum by a in one direction at each input of a first predetermined signal based on an input signal input to the frequency changing unit, where a is a natural number; and an output signal generating unit operable to output a second predetermined signal at each time at which the sum after being updated has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a, thereby generating the reference clock.
In the transmitter mentioned above, the modulation unit and the digital-analog converter are synchronized with the reference clock output from the reference clock generating unit.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.